OVM (Open Verification Methodology) is the currently most advanced
verification environment supported by the leading EDA companies
Mentor Graphics and Cadence.
Based on the object-oriented power of SystemVerilog, combined with a
sophisticated class- and reporting structure, OVM is an excellent foundation
to build your own library of drivers and monitors where necessary,
while providing inheritent support for all standard functions and features.
This way it is an excellent blend of guidance and freedom to do
what you need to do.
However, such power and flexibility does not come for free ...
You will need VHDL, Verilog and SystemVerilog knowledge, as well as a good
grasp of object-oriented software structures and class interfactions.
Our engineers have done their work and are up-to-speed, so let us help you
along your learning curve and get you productive fast. Whether with training,
design assistance, or contract verification work, we are here for you.