Verilog was first, a lot of legacy designs exist, and so does the need to maintain and expand them. It is also close to read hardware, easy to use, the main language for gate-level netlists and quick for small tasks.

Due to the work in SystemVerilog and physical-layer netlists, we are well familiar with the Verilog coding.

However, when starting any new project, design or even a small module, we rather recommend to use VHDL for all its power and benefits. We will gladly show you how easy it is to integrate VHDL blocks into Verilog designs or vice versa.

Let us worry about the syntax and coding - you have enough serious stuff on your mind ...


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