Standardized in IEEE 1800-2005, SystemVerilog is extending Verilog to be
not only a Hardware Description Language, but also a very powerful
Hardware Verification Language:

  • New data types
  • Multi-dimensional packed arrays, enumerated types, strucutres and unions, interfaces, associative arrays and queues
  • Classes
  • Inheritance model, polzmorhism, virtual methods, local and protected elements
  • Randomization
  • Pure random or constrained random generation, with autogenerated or external seed
  • Assertions
  • Built from sequences and properties, implication operation with antecendent and consequent clauses
  • Coverage
  • Automatic coverage analysis, which can control test execution and randomization
Let us help you as you navigate these new concepts !

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